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Low-, medium- and high-density reset and clock control (RCC)
Bit 23 USBRST: USB reset
Set and cleared by software.
0: No effect
1: Reset USB
Bit 22 I2C2RST: I2C 2 reset
Set and cleared by software.
0: No effect
1: Reset I2C 2
Bit 21 I2C1RST: I2C 1 reset
Set and cleared by software.
0: No effect
1: Reset I2C 1
Bit 20 UART5RST: USART 5 reset
Set and cleared by software.
0: No effect
1: Reset USART 5
Bit 19 UART4RST: USART 4 reset
Set and cleared by software.
0: No effect
1: Reset USART 4
Bit 18 USART3RST: USART 3 reset
Set and cleared by software.
0: No effect
1: Reset USART 3
Bit 17 USART2RST: USART 2 reset
Set and cleared by software.
0: No effect
1: Reset USART 2
RM0008
Bits 16
Reserved, always read as 0.
Bit 15 SPI3RST: SPI 3 reset
Set and cleared by software.
0: No effect
1: Reset SPI 3
Bit 14 SPI2RST: SPI 2 reset
Set and cleared by software.
0: No effect
1: Reset SPI 2
Bits 13:12
Reserved, always read as 0.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
92/995
Bits 10:6
Reserved, always read as 0.
Doc ID 13902 Rev 9
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